This invention relates to programmable logic integrated circuit devices, and more particularly to the organization of particular types of interconnection conductors on such devices.
Programmable logic devices with areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,689,195, which is hereby incorporated by reference herein in its entirety. Advances in integrated circuit fabrication technology are making it possible to make such programmable logic devices both larger and denser. For example, more and more areas of programmable logic can be put on such devices by making the device larger, or denser, or both larger and denser.
Many desired uses of programmable logic devices require certain signals to be supplied to many logic areas. For example, many logic areas may need to receive the same register clocking or register clearing ("control") signals. Or many areas may need to receive the same "data" signal. In some cases each of several data or control signals may need to go to respective different groups of logic areas, each such group including many areas. Some of the data or control signals requiring dispersion to many logic areas may need to come from outside the device, while others may need to be generated on the device.
Efficient networks are needed for allowing flexible distribution of very wide fan-out signals of the type described above. Because such a network must extend so extensively throughout the device, the number of conductors in the network should be kept relatively low to avoid devoting an undue proportion of the total resources of the device to these conductors and the connections from these conductors to each logic area on the device. The network should also preferably be designed for rapid dissemination of the signals on the network because these widely used signals should not hold back the operating speed of the device. In fact, a network of this type may be called a "fast conductor" or "fast signal" network to indicate the desirability of rapid propagation of signals on the network. The network should allow signals to reach any logic area on the device with relatively little delay, and there should also be relatively little "skew" associated with the network. (Skew refers to different amounts of delay being associated with reaching different logic areas on the device.)
In view of the foregoing, it is an object of this invention to provide improved fast conductor networks for programmable logic devices.
It is a more particular object of this invention to provide fast conductor networks which require relatively small amounts of the overall resources of the device, but which are capable of rapidly and flexibly distributing either external or internal signals throughout the device with relatively little skew.